In double data rate fourth generation (DDR4) and fifth generation (DDR5), a memory interface (i.e., a registered clock driver or a data buffer) is a source of synchronous data transportation between the host central processing unit (CPU) and the synchronous dynamic random-access memory (SDRAM) modules. Data transmission through a memory interface is bi-directional (i.e., read and write). In order to maintain a timing relationship, a total amount of delay through the memory buffer needs to be constant. The total amount of delay is often referred to as a propagation delay (tPDM) value. Furthermore, signals generated by SDRAM modules have a lot of noise.
The tPDM can be marginally varied around a specified value. The specified value for tPDM for an RCD is 1.2 ns. The specified value for tPDM for a data buffer is 1.5 ns. The conventional solutions use a phase-locked loop (PLL) or a delay-locked loop (DLL) to lock the timing relationship and keep tPDM constant. Conventional solutions also use a delay line and phase blender to adjust the skew to correct pin-to-pin variation due to the layout matching and process, voltage and temperature (PVT) variation.
Conventional circuitry for making tPDM constant is very complicated. Many clock phases need to be generated which makes the timing critical and sensitive to the process. To close the timing using conventional circuitry is very difficult. Furthermore, with a DLL/PLL solution, there is a limitation on the loop bandwidth. For DDR5, with the data rates increasing to 4.4 GHz, 6.6 GHz and higher, loop bandwidth limitation due to PLL/DLL will cause design challenges. Since conventional circuitry uses PLL/DLL internally for phase alignment and to lock all the signals, there are problems when scaling down the process size. The PLL/DLL also consumes a large amount of power.
It would be desirable to implement an open loop solution in data buffer and RCD.